Semiconductor manufacturers currently employ two primary technologies for central processing unit (CPU) packages. The first is referred to as pin grid array (PGA) sockets and the second is commonly referred to as land grid array (LGA) sockets.
PGA packages typically have a greater assembly and material cost due to the pins. In addition, there are limitations on the pin pitch and number of pins that can realistically be manufactured.
LGA packages may be less costly since there may be no holes, rather, pins on the LGA touch contact points on the underside of the CPU and are retained in the socket by either an integral loading scheme such as the direct socket loading (DSL) for socket T or an independent loading mechanism (ILM) with a back plate as adopted for socket B. Socket T and Socket B refer to two types of currently used socket variations.
Unfortunately, the DSL mechanism may result in solder joint reliability issues in various shock, vibration and power cycle conditions. In addition, it may pose challenges with scalability to accommodate larger numbers of contacts and may not easily lend itself to low profile designs.
The ILM, on the other hand, utilizes a back plate which may render it less desirable in system designs that have minimal clearance between the back of the board and the chassis. Another disadvantage of the ILM design is that it is an additional part that adds to the total cost of the system.
Thus, semiconductor manufacturers are constantly striving to find affordable new ways to secure a CPU reliably in a confined area.